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1 for more information www.linear.com/lTC2945 typical a pplica t ion fea t ures descrip t ion wide range i 2 c power monitor wide range power monitor with onboard adc and i 2 c a pplica t ions n rail-to-rail input range: 0v to 80v n wide input supply range: 2.7v to 80v n shunt regulator for supplies >80v n ? adc with less than 0.75% total unadjusted error n 12-bit resolution for current and voltages n internal multiplier calculates 24-bit power value n stores minimum and maximum values n alerts when limits exceeded n additional adc input monitors an external voltage n continuous scan and snapshot modes n shutdown mode with i q < 80a n split sda for opto-isolation n available in 12-lead 3mm 3mm qfn and msop packages n telecom infrastructure n industrial n automotive n consumer l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. i 2 c interface nine i 2 c addresses sense + sense ? alert scl sdai sdao adin v dd intv cc adr1 adr0 gnd lTC2945 measured voltage to load 0.1f 0.02 v in 4v to 80v 2945 ta01 adc differential nonlinearity (adin) adc integral nonlinearity (adin) the lt c ? 2945 is a rail-to-rail system monitor that mea - sures current, voltage, and power. it features an operating range of 2.7v to 80v and includes a shunt regulator for supplies above 80v to allow flexibility in the selection of input supply. the current measurement range of 0v to 80v is independent of the input supply. an onboard 0.75% accurate 12-bit adc measures load current, input voltage and an auxiliary external voltage. a 24-bit power value is generated by digitally multiplying the measured 12-bit load current and input voltage data. minimum and maximum values are stored and an overrange alert with program - mable thresholds minimizes the need for software polling. data is reported via a standard i 2 c interface. shutdown mode reduces power consumption to 20a. the lTC2945 i 2 c interface includes separate data input and output pins for use with standard or opto-isolated i 2 c connections. the lTC2945-1 has an inverted data output for use with inverting opto-isolator configurations. code 0 ?0.3 adc dnl (lsb) 0.3 0.0 0.1 0.2 ?0.2 ?0.1 3072 4096 1024 2048 2945 ta01a code 0 ?0.3 adc inl (lsb) 0.3 0.0 0.1 0.2 ?0.2 ?0.1 3072 4096 1024 2048 2945 ta01b lTC2945 2945fa
2 for more information www.linear.com/lTC2945 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v dd voltage .............................................. C 0.3v to 100v sense + voltage ........................................... C 1v to 100v sense C voltage ..... C1 v or sense + C 1v to sense + + 1v intv cc voltage (note 3) ........................... C 0.3v to 5.9v adr1, adr0, adin, alert , sdao, sdao voltage ......................................................... C 0.3v to 7v intv cc clamp current ........................................... 3 5ma (notes 1, 2) lTC2945 12 11 10 4 5 6 top view 13 ud package 12-lead (3mm 3mm) plastic qfn 7 8 9 3 2 1intv cc adr1 adr0 alert sdao sdai v dd sense + sense ? adin gnd scl t jmax = 125c, q ja = 58.7c/w exposed pad (pin 13) pcb gnd connection optional 1 2 3 4 5 6 v dd intv cc adr1 adr0 adin gnd 12 11 10 9 8 7 sense + sense ? alert sdao sdai scl top view ms package 12-lead plastic msop t jmax = 125c, q ja = 135c/w lTC2945-1 12 11 10 4 5 6 top view 13 ud package 12-lead (3mm 3mm) plastic qfn 7 8 9 3 2 1intv cc adr1 adr0 alert sdao sdai v dd sense + sense ? adin gnd scl t jmax = 125c, q ja = 58.7c/w exposed pad (pin 13) pcb gnd connection optional 1 2 3 4 5 6 v dd intv cc adr1 adr0 adin gnd 12 11 10 9 8 7 sense + sense ? alert sdao sdai scl top view ms package 12-lead plastic msop t jmax = 125c, q ja = 135c/w scl, sdai voltages (note 4) ..................... C0 .3v to 5.9v scl, sdai clamp current ........................................ 5m a operating temperature range lt c2945c ................................................ 0 c to 70c lt c2945i ............................................. C4 0c to 85c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10sec) ms p ackage only .............................................. 3 00c lTC2945 2945fa
3 for more information www.linear.com/lTC2945 o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range lTC2945cud#pbf lTC2945cud#trpbf lfwk 12-lead (3mm 3mm) plastic qfn 0c to 70c lTC2945iud#pbf lTC2945iud#trpbf lfwk 12-lead (3mm 3mm) plastic qfn C40c to 85c lTC2945cud-1#pbf lTC2945cud-1#trpbf lfyx 12-lead (3mm 3mm) plastic qfn 0c to 70c lTC2945iud-1#pbf lTC2945iud-1#trpbf lfyx 12-lead (3mm 3mm) plastic qfn C40c to 85c lTC2945cms#pbf lTC2945cms#trpbf 2945 12-lead plastic msop 0c to 70c lTC2945ims#pbf lTC2945ims#trpbf 2945 12-lead plastic msop C40c to 85c lTC2945cms-1#pbf lTC2945cms-1#trpbf 29451 12-lead plastic msop 0c to 70c lTC2945ims-1#pbf lTC2945ims-1#trpbf 29451 12-lead plastic msop C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www .linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ e lec t rical c harac t eris t ics symbol parameter conditions min typ max units supplies v dd v dd supply voltage range l 4 80 v v intvcc intv cc supply voltage range l 2.7 5.9 v i dd v dd supply current v dd = 48v, intv cc open shutdown l l 0.8 40 1.2 70 ma a i cc intv cc supply current intv cc = v dd = 5v shutdown, intv cc = v dd = 5v l l 0.6 20 0.9 80 ma a i ccsrc intv cc linear regulator output current v dd = 7v l C10 ma v cc intv cc linear regulator voltage 7v < v dd < 80v, i load = 1ma l 4.5 5 5.5 v v cc intv cc linear regulator load regulation 7v < v dd < 80v, i load = 1ma to 10ma l 100 200 mv v ccz intv cc shunt regulator voltage v dd = 48v, i cc = 1ma l 5.9 6.3 6.7 v v ccz intv cc shunt regulator load regulation v dd = 48v, i cc = 1ma to 35ma l 250 mv v cc(uvl) intv cc supply undervoltage lockout intv cc rising, v dd = intv cc l 2.2 2.6 2.69 v v dd(uvl) v dd supply undervoltage lockout v dd rising, intv cc open l 2.9 3.2 3.5 v v ddi2c(rst) v dd i 2 c logic reset v dd falling, intv cc open l 2 2.5 v v cci2c(rst) intv cc i 2 c logic reset intv cc falling, v dd = intv cc l 1.5 1.8 v sense inputs v cm sense + , sense C common mode voltage l 0 80 v i sense + (hi) 48v sense + input current sense + , sense C , v dd = 48v shutdown l l 100 150 2 a a i sense C (hi) 48v sense C input current sense + , sense C , v dd = 48v shutdown l l 20 1 a a i sense + (lo) 0v sense + source current sense + , sense C = 0v v dd = 48v shutdown l l C10 C2 a a i sense C (lo) 0v sense C source current sense + , sense C = 0v, v dd = 48v shutdown l l C5 1 a a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v dd is from 4v to 80v unless otherwise noted. (note 2) lTC2945 2945fa
4 for more information www.linear.com/lTC2945 symbol parameter conditions min typ max units adc res resolution (no missing codes) (note 5) l 12 bits v fs full-scale voltage sense (note 7) v in adin l l l 101.7 101.7 2.033 102.4 102.4 2.048 103.1 103.1 2.063 mv v v lsb lsb step size sense v in adin 25 25 0.5 v mv mv tue t otal unadjusted error (note 6) sense v in adin l l l 0.75 0.75 0.75 % % % v os offset error sense v in adin l l l 3.1 1.5 1.1 lsb lsb lsb inl integral nonlinearity sense v in adin l l l 3 2 2 lsb lsb lsb s t transition noise (note 5) sense v in adin 1.2 0.3 10 v rms mv rms v rms f conv conversion rate (continuous mode) l 6 7.5 9 hz t conv conversion time (snapshot mode) sense v in , adin l l 60 30 66 33 72 36 ms ms r adin adin pin input resistance v dd = 48v, adin = 3v l 3 10 m i adin adin pin input current v dd = 48v, adin = 3v l 1 a i 2 c interface (v dd = 48v) v adr(h) adr0, adr1 input high threshold l 2.1 2.4 2.7 v v adr(l) adr0, adr1 input low threshold l 0.3 0.6 0.9 v i adr(in) adr0, adr1 input current adr0, adr1 = 0v, 3v l 13 a i adr(in,z) allowable leakage when open l 7 a v od(ol) sdao, sdao, alert output low voltage i sdao , i sdao , i alert = 8ma l 0.15 0.4 v i sda,scl(in) sdai, sdao, sdao , scl input current sdai, sdao, sdao, scl = 5v l 0 1 a v sda,scl(th) sdai, scl input threshold l 1.5 1.9 2.2 v v sda,scl(cl) sdai, scl clamp voltage i sdai , i scl = 3ma l 5.9 6.4 6.9 v i alert (in) alert input current alert = 5v l 0 1 a e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v dd is from 4v to 80v unless otherwise noted. (note 2) lTC2945 2945fa
5 for more information www.linear.com/lTC2945 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive. all voltages are referenced to ground, unless otherwise noted. note 3: an internal shunt regulator limits the intv cc pin to a minimum of 5.9v. driving this pin to voltages beyond 5.9v may damage the part. this pin can be safely tied to higher voltages through a resistor that limits the current below 35ma. symbol parameter conditions min typ max units i 2 c interface timing f scl(max) maximum scl clock frequency 400 khz t low minimum scl low period 0.65 1.3 s t high minimum scl high period 50 600 ns t buf(min) minimum bus free time between stop/start condition 0.12 1.3 s t hd,sta(min) minimum hold time after (repeated) start condition 140 600 ns t su,sta(min) minimum repeated start condition set-up time 30 600 ns t su,sto(min) minimum stop condition set-up time 30 600 ns t hd,dati(min) minimum data hold time input C100 0 ns t hd,dato(min) minimum data hold time output 300 600 900 ns t su,dat(min) minimum data set-up time 30 100 ns t sp(max) maximum suppressed spike pulse width 50 110 250 ns t rst stuck bus reset time scl or sdai held low 25 33 ms c x scl, sdai input capacitance (note 5) 5 10 pf e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v dd is from 4v to 80v unless otherwise noted. (note 2) note 4: internal clamps limit the scl and sdai pins to a minimum of 5.9v. driving these pins to voltages beyond the clamp may damage the part. the pins can be safely tied to higher voltages through resistors that limit the current below 5ma. note 5: guaranteed by design and not subject to test. note 6: t ue = actual code ? ideal code ( ) 4096 100 % where ideal code is derived from a straight line passing through code 0 at 0v and theoretical code of 4096 at v fs . note 7: sense is defined as v sense + C v sense C lTC2945 2945fa
6 for more information www.linear.com/lTC2945 typical p er f or m ance c harac t eris t ics intv cc supply current in shutdown intv cc load regulation intv cc line regulation adc integral nonlinearity (adin) adc differential nonlinearity (adin) adc total unadjusted error (adin) v dd supply current v dd supply current in shutdown intv cc supply current v dd = 48v, t a = 25c, unless noted. v dd supply voltage (v) 0 600 supply current (a) 800 750 700 650 60 80 20 40 2945 g01 v dd supply voltage (v) 0 10 supply current (a) 70 60 40 50 20 30 60 80 20 40 2945 g02 v cc supply voltage (v) 2 500 supply current (a) 600 575 525 550 5 6 3 4 2945 g03 v cc supply voltage (v) 2 10.0 supply current (a) 22.5 17.5 20.0 12.5 15.0 5 6 3 4 2945 g04 code 0 ?0.3 adc inl (lsb) 0.3 0.0 0.1 0.2 ?0.2 ?0.1 3072 4096 1024 2048 2945 g07 code 0 ?0.3 adc dnl (lsb) 0.3 0.0 0.1 0.2 ?0.2 ?0.1 3072 4096 1024 2048 2945 g08 code 0 ?0.02 adc total unadjusted error (%) 0.02 0.01 ?0.01 0 3072 4096 1024 2048 2945 g09 load current (ma) 0 4.8 intv cc voltage (v) 5.2 5.1 4.9 5.0 86 10 2 4 2945 g05 v dd supply volyage (v) 0 3.0 intv cc voltage (v) 5.5 4.5 5.0 3.5 4.0 60 40 80 20 2945 g06 lTC2945 2945fa
7 for more information www.linear.com/lTC2945 typical p er f or m ance c harac t eris t ics sdao, sdao, alert loaded output low voltage sense + input current scl, sdai loaded clamp voltage sense C input current intv cc shunt regulator load regulation adro, adr1 voltage with current sink or source adc integral nonlinearity ( sense) adc differential nonlinearity ( sense) adc t otal unadjusted error ( sense) v dd = 48v, t a = 25c, unless noted. code 0 ?0.4 adc inl (lsb) 0.4 0.2 ?0.2 0.0 3072 4096 1024 2048 2945 g10 code 0 ?0.3 adc dnl (lsb) 0.3 0.0 0.1 0.2 ?0.2 ?0.1 3072 4096 1024 2048 2945 g11 code 0 ?0.50 adc total unadjusted error (%) 0.50 0.25 ?0.25 0.00 3072 4096 1024 2048 2945 g12 i sda , alert (ma) 0 0.0 v sda , alert(ol) (v) 0.4 0.3 0.1 0.2 8 10 2 4 6 2945 g13 i load (ma) 0.01 6.0 v sda , scl(cl) (v) 6.6 6.5 6.1 6.2 6.3 6.4 10.00 0.10 1.00 2945 g14 v sense + (v) 0 ?10 i sense + (a) 150 110 30 70 80 20 40 60 2945 g16 v sense + (v) 0 ?2 i sense ? (a) 10 8 6 0 4 2 80 20 40 60 2945 g17 i adr (a) ?10 0.0 v adr (v) 3.0 2.5 2.0 0.5 1.5 1.0 10 ?5 0 5 2945 g18 v cc shunt current (ma) 0 6.0 intv cc voltage (v) 6.6 6.4 6.2 30 40 10 20 2945 g15 lTC2945 2945fa
8 for more information www.linear.com/lTC2945 p in func t ions adin: adc input. the onboard adc measures voltages between 0v and 2.048v. tie to ground if unused. adr1, adr0: i 2 c device address inputs. connecting these pins to intv cc , gnd or leaving the pins open configures one of nine possible addresses. see table 1 in applications information section for details. alert : fault alert output. open drain logic output that is pulled to ground after an adc conversion resulted in a fault to alert the host controller. a fault alert is enabled by setting the corresponding bit in the alert register as shown in table 4. this device is compatible with the smbus alert protocol. see applications information. tie to ground if unused. exposed pad (pin 13, dd package only): exposed pad may be left open or connected to device ground. for best thermal performance, connect to a large pcb area. gnd: device ground. intv cc : internal low voltage supply input/output. this pin is used to power internal circuitry. it can be config - ured as a direct input for a low voltage supply, as linear regulator from higher voltage supply connected to v dd , or as a shunt regulator. connect this pin directly to a 2.7v to 5.9v supply if available. when intv cc is powered from an external supply, short the v dd pin to intv cc . if v dd is connected to a 4v to 80v supply, intv cc becomes the 5v output of an internal series regulator that can supply up to 10ma to external circuitry. for even higher supply voltages or if a floating topology is desired, intv cc can be used as a 6.3v shunt regulator. connect the supply to intv cc through a shunt resistor that limits the current to less than 35ma. an undervoltage lockout circuit disables the adc when the voltage at this pin drops below 2.5v. connect a bypass capacitor between 0.1f and 1f from this pin to ground. scl: i 2 c bus clock input. data at the sdai pin is shifted in or out on rising edges of scl. this pin is driven by an open-collector output from a master controller. an external pull-up resistor or current source is required and can be placed between scl and v dd or intv cc . the voltage at scl is internally clamped to 6.4v (5.9v minimum) sdai: i 2 c bus data input. used for shifting in address, command or data bits. this pin is driven by an open- collector output from a master controller. an external pull-up resistor or current source is required and can be placed between sdai and v dd or intv cc . the voltage at sdai is internally clamped to 6.4v (5.9v minimum) sdao: i 2 c bus data output. open-drain output used for sending data back to the master controller or acknowledging a write operation. an external pull-up resistor or current source is required. sdao: inverted i 2 c bus data output. open-drain output used for sending data back to the master controller or acknowledging a write operation. data is inverted for convenience of opto-isolation. an external pull-up resistor or current source is required. sense + : supply voltage and current sense input. used as a supply and current sense input for the internal current sense amplifier. the voltage at this pin is monitored by the onboard adc with a full-scale input range of 102.4v. see figure 16 for recommended kelvin connection. sense C : current sense input. connect an external sense resistor between sense + and sense C . the differential voltage between sense + and sense C is monitored by the onboard adc with a full-scale sense voltage of 102.4mv. v dd : high voltage supply input. this pin powers an internal series regulator with input voltages ranging from 4v to 80v and produces 5v at intv cc when the input voltage is above 7v. connect a bypass capacitor between 0.1f and 1f from this pin to ground if external load is pres - ent on the intv cc pin. the onboard 12-bit adc can be configured to monitor the voltage at v dd with a full-scale input range of 102.4v. lTC2945 2945fa
9 for more information www.linear.com/lTC2945 b lock diagra m 2945 bd v dd sense + 20x 5.7v 735k + ? 15k 6.3v gnd intv cc sense ? adin adr1 adr0 alert mux 12-bit adc decoder v ref = 2.048v sdao/sdao sdai scl i c 2 12 735k 15k (lTC2945 / lTC2945-1) 6.4v 6.4v logic registers v stby v stby gen v stby lTC2945 2945fa
10 for more information www.linear.com/lTC2945 ti m ing diagra m t sp t buf t su,sto t sp t hd,sta start condition stop condition t su,sta t hd,dati t hd,dato repeated start condition repeated start condition t su,dat sda scl t hd,sta 2945 td lTC2945 2945fa
11 for more information www.linear.com/lTC2945 2945 f01 c2 0.1f v in 4v to 80v r sns 0.02 v out v adin r1 2k r2 2k r3 2k 3.3v v dd scl sda int gnd adr0 scl v dd intv cc sdai sdao adin alert adr1 sense + gnd sense ? lTC2945 p figure 1. monitoring high side current and voltages using the lTC2945 the lTC2945 offers a compact and complete solution for high- and low-side power monitoring. with an input com - mon mode range of 0v to 80v and a wide input supply operating voltage range from 2.7v to 80v , this device is ideal for a large variety of power management applications including automotive, industrial and telecom infrastructure. the basic application circuit shown in figure 1 provides monitoring of high side current with a 0.02 resistor (5.12a full-scale), input voltage (102.4v full-scale) and an external voltage (2.048v full-scale), all using an internal 12-bit resolution adc. data converter the lTC2945 features an onboard, 12-bit ? adc that inher - ently averages input noise over the measurement window. the adc continuously monitors three voltages in sequence: sense first, v dd or v sense + second, and v adin third. the differential voltage between sense + and sense C is moni- tored with 25v resolution (102.4mv full-scale) to allow accurate measurement across ver y low value shunt resistors. a pplica t ions i n f or m a t ion the supply voltage at v dd or sense + is directly measured with 25mv resolution (102.4v full-scale). the voltage at the uncommitted adin pin is measured with 0.5mv resolu - tion (2.048v full-scale) to allow monitoring of an arbitrary external voltage. a 12-bit digital word corresponding to each measured voltage is stored in two adjacent registers o pera t ion the lTC2945 accurately monitors current, voltage, and power of any supply rail from 0v to 80v. an internal linear regulator allows the lTC2945 to operate directly from a 4v to 80v rail, or from an external supply voltage between 2.7v and 5.9v. quiescent current is less than 0.9ma in normal operation. enabling shutdown mode via the i 2 c interface reduces the quiescent current to below 80a. the lTC2945 includes a shunt regulator for operation from supply voltages above 80v. the onboard 12-bit analog-to-digital converter (adc) runs either continuously or on-demand using snapshot mode. in the default continuous scan mode, the adc repeatedly measures the differential voltage between sense + and sense C (full-scale 102.4mv) the voltage at the sense + or v dd pin (full-scale 102.4v), and the voltage at the adin pin (full-scale 2.048v). the conversion results are stored in onboard registers. in snapshot mode, the lTC2945 performs a single mea - surement of one selected voltage or current. snapshot mode is enabled by setting the snapshot mode enable bit in the control register via the i 2 c interface. a status bit in the control register monitors the adcs conversion; when complete, the conversion result is stored in the cor - responding data registers. onboard logic tracks the minimum and maximum values for each adc measurement, calculates power data by digitally multiplying the stored current and voltage data, and triggers a user-configurable alert by pulling the alert pin low when the adc measured value falls outside the programmed window thresholds. all logic outputs are stored in onboard registers. the lTC2945 includes an i 2 c interface to access the onboard data registers and to program the alert threshold and control registers. two three-state pins, adr1 and adr0, are decoded to allow nine device addresses (see table 1). the sda pin is split into sdai (input) and sdao (output, lTC2945) or sdao (output, lTC2945-1) to facilitate opto-isolation. lTC2945 2945fa
12 for more information www.linear.com/lTC2945 sense pins can be biased independent of the parts supply voltage. alternatively, if a low voltage supply is present it can be connected to the intv cc pin as shown in figure 2c to minimize on-chip power dissipation. when intv cc is powered from a secondary supply, connect v dd to intv cc . for supply voltages above 80v, the shunt regulator at intv cc can be used in both high and low side configura - tions to provide power to the lTC2945 through an external shunt resistor , r shunt . figure 3a shows a high side power monitor with an input monitoring range beyond 80v in a high side shunt regulator configuration. the device ground is separated from ground through r shunt and clamped at 6.3v below the input supply. note that due to the different ground levels, the i 2 c signals from the part need to be level shifted for communication with other ground referenced components. the bus voltage can be measured with the adin pin as shown in figure 3a. to mitigate the effect of v be mismatch in the pnp mirror, select r1 (=r2) to drop 1v at the operating voltage. for details on the power calculation, refer to the power calculation and configuration section. figure 3b shows a high side rail-to-rail power monitor which derives power from a greater than 80v secondary supply. the voltage at intv cc is clamped at 6.3v above ground in a low side shunt regulator configuration to power the part. in low side power monitors, the device ground and the current sense inputs are connected to the negative terminal of the input supply and the adin pin can be used to measure the bus voltage with an external resistive divider as shown in figure 3c. the low side shunt regulator configuration allows operation with input supplies above 80v by clamping the voltage at intv cc . r shunt should be sized according to the following equation: v s(max ) C 5.9v 35ma r shunt v s(min) C 6.7v 1ma + i load(max ) where v s(max) and v s(min) are the operating maximum and minimum of the supply. i load(max) is the maximum external current load that is connected to the shunt regula - tor. the shunt resistor must also be rated to safely dissipate the worst-case power . as an example, consider the C 48v telecom system where the supply operates from C36v to C72v and the shunt regulator is used to supply an external load up to 4ma. r shunt needs to be between 1.9k and 5.9k according to the above equation, and for reduced a pplica t ions i n f or m a t ion out of the six total adc data registers ( sense msb/lsb, v in msb/lsb, and adin msb/lsb), with the eight msbs in the first register and the four lsbs in the second (see table 2). the lowest 4 bits in the lsb registers are set to 0. these data registers are updated immediately following the corresponding adc conversion, giving an effective refresh rate of 7.5hz in continuous scan mode. the data converter also features a snapshot mode which makes a measurement of a single selected voltage (either sense, v dd or v sense +, or v adin ). to make a snapshot measurement, set control register bit a7 and write the two-bit code of the desired adc channel to a6 and a5 (table 3) using a write byte command. when the write byte com - mand is completed, the adc converts the selected voltage and the busy bit (a3 in the control register) will be set to indicate that the conversion is in progress. after completing the conversion, the adc will halt and the busy bit will reset to indicate that the data is ready. to make another snapshot measurement, rewrite the control register. flexible power supply to lTC2945 the lTC2945 can be externally configured to flexibly derive power from a wide range of supplies. the lTC2945 includes an onboard linear regulator to power the low-voltage internal circuitry connected to the intv cc pin from high v dd voltages. the regulator operates with v dd voltages from 4v to 80v, and produces a 5v output capable of supplying 10ma at the intv cc pin when v dd is greater than 7v. the regulator is disabled when die temperature rises above 150c, and the output is protected against accidental shorts. bypass capaci - tors between 0.1f and 1f at both the v dd and intv cc pins are recommended for optimal transient performance. note that operation with high v dd voltages can cause significant power dissipation, and care is required to ensure the operating junction temperature stays below 125c. for improved power dissipation, use the qfn package and solder the exposed pad to a large copper region for improved thermal resistance. figure 2a shows the lTC2945 being used to monitor an input supply that ranges from 4v to 80v. no secondary supply is needed since v dd can be connected directly to the input supply. if the lTC2945 is used to monitor an input supply of 0v to 80v, it can derive power from a wide range secondary supply connected to the v dd pin as shown in figure 2b. the (1) lTC2945 2945fa
13 for more information www.linear.com/lTC2945 a pplica t ions i n f or m a t ion c2 v in 4v to 80v r sns v out v dd intv cc sense + gnd 2945 f02a sense ? lTC2945 c2 v in 0v to 80v 4v to 80v r sns v out v dd intv cc sense + gnd 2945 f02b sense ? lTC2945 v in 0v to 80v 2.7v to 5.9v c2 r sns v out v dd intv cc sense + gnd 2945 f02c sense ? lTC2945 figure 2a. lTC2945 derives power from the supply being monitored figure 3a. lTC2945 derives power through high-side shunt regulator figure 3b. lTC2945 derives power through low-side shunt regulator in high-side current sense topology figure 2b. lTC2945 derives power from a wide range secondary supply figure 2c. lTC2945 derives power from a low voltage secondary supply gnd c2 r1 r2 v neg > ?80v r sns v out v dd r shunt intv cc sense ? gnd adin 2945 f03a sense + lTC2945 figure 3c. lTC2945 derives power through low-side shunt regulator in low-side current sense topology v in >80v r 4 r 2 r shunt adin q1 gnd 2945 f03a lTC2945 r 3 r 1 intv cc r sns sense + sense ? v in 0v to 80v >80v c2 r sns v out r shunt v dd intv cc sense + gnd 2945 f03b sense ? lTC2945 lTC2945 2945fa
14 for more information www.linear.com/lTC2945 a pplica t ions i n f or m a t ion gnd c2 v neg ?4v to ?80v r sns v out v dd intv cc sense ? gnd 2945 f03b sense + lTC2945 figure 3d. lTC2945 derives power from the supply being monitored in low-side current sense topology power dissipation, a larger resistance is advantageous. the worst-case power dissipated in an r shunt of 5.4k is calculated to be 0.8w. so, three 0.5w rated 1.8k resistors in series would suffice for this example. if the supply input is nominally below 80v and transient is limited to below 100v, the shunt resistor is not required and v dd can be connected to gnd of the supply as shown in figure 3d. supply undervoltage lockout during power-up, the internal i 2 c logic and the adc are enabled when either v dd or intv cc rises above its under - voltage lockout threshold. during power-down, the adc is disabled when v dd and intv cc fall below their respective undervoltage lockout thresholds. the internal i 2 c logic is reset when v dd and intv cc fall below their respective i 2 c reset thresholds. shutdown mode the lTC2945 includes a low quiescent current shutdown mode, controlled by bit a1 in the control register (table 3). setting a1 puts the part in shutdown mode, powering down the adc and internal reference. the internal i 2 c bus remains active, and although the adr1 and adr0 pins are disabled, the device will retain the most recently programmed i 2 c bus address. all on-board registers re - tain their contents and can be accessed through the i 2 c interface. to re-enable adc conversions, reset bit a1 in the control register. the analog circuitry will power up and all registers will retain their contents. the onboard linear regulator is disabled in shutdown mode to conserve power. if low i q mode is not required and the regulator is used to power i 2 c bus-related circuitry such as opto-couplers or pull-ups, ensure bit a1 in the control register is masked off during software development. in such applications, the user is advised that accidentally disabling the regulator would prevent i 2 c communication from the master and cause the lTC2945 to disengage from the system. the lTC2945 would then have to be reset by cycling its power to come out of shutdown. it is recommended that external regulators be used in such applications if powering down the lTC2945 is desirable. quiescent current drops below 80a in shutdown mode with the internal regulator disabled. power calculation and configuration the lTC2945 calculates power by multiplying the measured current with the measured voltage. in continuous mode, the differential voltage between sense + and sense C is measured to obtain load current data. the supply voltage data for mul - tiplication can be selected between v dd , sense + , or adin. sense + is selected by default as it is normally connected to the supply voltage. in negative supply voltage systems such as shown in figure 3d, the device ground (gnd pin of lTC2945) and sense C are connected to the supply and v dd measures the supply voltage at gnd with respect to the device ground. for negative supply voltages of more than 80v, use external resistors to divide down the voltage to suit the adin measurement range. in the control register, ? write bits a2=1, a0=1 to select sense + (default) ? write bits a2=0, a0=1 to select v dd ? write bits a2=1, a0=0 to select adin more details on the control register can be found in table 3. once the adc conversions are complete, a 24-bit power value is generated by digitally multiplying the 12-bit load current data with the 12-bit supply voltage data. 1lsb of power is 1lsb of voltage multiplied by 1lsb of sense (current). the result is held in the three adjacent power registers (t able 2). the power registers initialize with undefined data and subsequently refresh at a frequency of 7.5hz in continuous scan mode. in snapshot mode, the power registers are not refreshed. lTC2945 2945fa
15 for more information www.linear.com/lTC2945 a pplica t ions i n f or m a t ion storing minimum and maximum values the lTC2945 compares each measurement including the calculated power with the stored values in the respective min and max registers for each parameter (table 2). if the new conversion is beyond the stored minimum or maximum values, the min or max registers are updated with the new values. the min and max of the registers are refreshed at the end of their respective adc conversions in both continuous scan mode and snapshot mode. they are also refreshed if the adc registers are written via the i 2 c bus with values beyond the stored values. to initiate a new peak hold cycle, write all 1s to the min registers and all 0s to the max registers via the i 2 c bus. these registers will be updated when the next respective adc conversion is done. the lTC2945 also includes min and max threshold registers (table 2) for the measured parameters including the calculated power. at power-up, the maximum thresh - olds are set to all 1s and minimum thresholds are set to all 0s, effectively disabling them. the thresholds can be reprogrammed to any desired value via the i 2 c bus. fault alert and resetting faults as soon as a measured quantity falls below the minimum threshold or exceeds the maximum threshold, the lTC2945 sets the corresponding flag in the status register and latches it into the fault register (see figure 4). the alert pin is pulled low if the appropriate bit in the alert register is set. more details on the alert behavior can be found in the alert response protocol section. an active fault indication can be reset by writing zeros to the corresponding fault register bits or by reading the fault cor register (table 2), which clears all fault register bits. all fault register bits are also cleared if the v dd and intv cc fall below their respective i 2 c logic reset threshold. note that faults that are still present, as indi - cated in the status registers, will immediately reappear. i 2 c interface the lTC2945 includes an i 2 c/smbus-compatible inter - face to provide access to the onboard registers. figure 5 shows a general data transfer format using the i 2 c bus. the lTC2945 is a read-write slave device and supports the smbus read byte, write byte, read word and write word protocols. the lTC2945 also supports extended read and write commands that allow reading or writing more than two bytes of data. when using the read/write word or extended read and write commands, the bus master issues an initial register address and the internal register address pointer automatically increments by 1 after each byte of data is read or written. after the register address reaches 31h, it will roll over to 00h and continue incrementing. a stop condition resets the register address pointer to 00h. the data formats for the above commands are shown in figures 6 to 11. i 2 c device addressing nine distinct i 2 c bus addresses are configurable using the three-state pins adr0 and adr1, as shown in table 1. adr0 and adr1 should be tied to intv cc , to gnd, or left floating (nc) to configure the lower four address bits. during low power shutdown, the address select state is latched into memory powered from standby supply. address bits a6, a5 and a4 are permanently set to (110) and the least significant bit is the r/w bit. in addition, all lTC2945 devices will respond to a common mass write address (1100 110)b; this allows the bus master to write to several lTC2945s simultaneously, regardless of their individual address settings. the lTC2945 will also respond to the standard ara address (0001100)b if the alert pin is asserted; see the alert response protocol section for more details. the lTC2945 will not respond to the ara address if no alerts are pending. start and stop conditions when the i 2 c bus is idle, both scl and sda are in the high state. a bus master signals the beginning of a transmission with a start condition by transitioning sda from high to low while scl stays high. when the master has finished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl stays high. the bus is then free for another transmission. lTC2945 2945fa
16 for more information www.linear.com/lTC2945 figure 4. lTC2945 fault alert generation blocks a pplica t ions i n f or m a t ion figure 5. general data transfer over i 2 c digital comparator logic latch status reset fault alert ena_alert_response measured data threshold data 2945 f04 sda scl s p a6 - a0 b7 - b0 b7 - b0 1 - 7 1 - 7 1 - 7 8 8 8 9 9 9 start condition stop condition address ack data data ack ack r/w 2945 f05 figure 6. lTC2945 serial bus sda write byte protocol figure 7. lTC2945 serial bus sda write word protocol figure 8. lTC2945 serial bus sda write page protocol figure 9. lTC2945 serial bus sda read byte protocol figure 10. lTC2945 serial bus sda read word protocol figure 11. lTC2945 serial bus sda read page protocol s address 1 1 0 a3:a0 from master to slave from slave to master a: acknowledge (low) a: not acknowledge (high) r: read bit (high) command d ata x x b5:b0 0 w 0 0 0b7:b0 a a a p 2945 f06 w: write bit (low) s: start condition p: stop condition s address 1 1 0 a3:a0 command d ata d ata x x b5:b0 0 w 0 0 0 0 2945 f07 b7:b0 b7:b0 a a a a p s address 1 1 0 a3:a0 command 0 x x b5:b0 0 w 0 0 2945 f08 a a a p b7:b0 d ata 0 a b7:b0 d ata 0 a ... ... b7:b0 d ata s address 1 1 0 a3:a0 1 1 0 a3:a0 1 0 command s address r a b7:b0 1 d ata x x b5:b0 0 w 0 0 2945 f09 a a a p s address 1 1 0 a3:a0 1 1 0 a3:a0 1 0 command s address r a b7:b0 1 d ata x x b5:b0 0 w 0 0 2945 f10 a 0 a b7:b0 d ata a a p s address 1 1 0 a3:a0 1 1 0 a3:a0 1 0 command s address r a b7:b0 1 d ata x x b5:b0 0 w 0 0 2945 f11 a 0 a b7:b0 d ata a a p ... ... b7:b0 d ata lTC2945 2945fa
17 for more information www.linear.com/lTC2945 a pplica t ions i n f or m a t ion stuck-bus reset the lTC2945 i 2 c interface features a stuck bus reset timer to prevent it from holding the bus lines low indefinitely if the scl signal is interrupted during a transfer. the timer starts when either scl or sdai is low, and resets when both scl and sdai are pulled high. if either scl or sdai are low for over 33ms, the stuck-bus timer will expire and the internal i 2 c interface and the sdao pin pulldown logic will be reset to release the bus. normal communication will resume at the next start command. acknowledge the acknowledge signal is used for handshaking between the transmitter and the receiver to indicate that the last byte of data was received. the transmitter always releases the sda line during the acknowledge clock pulse. the lTC2945 will pull the sda line low on the 9th clock cycle to acknowledge receipt of the data. if the slave fails to acknowledge by leaving sda high, then the master can abort the transmission by generating a stop condition. when the master is receiving data from the slave, the master must acknowledge the slave by pulling down the sda line during the 9th clock pulse to indicate receipt of a data byte. after the last byte has been received by the master, it will leave the sda line high (not acknowledge) and issue a stop condition to terminate the transmission. write protocol the master begins a write operation with a start condition followed by the seven-bit slave address and the r/w bit set to zero. after the addressed lTC2945 acknowledges the address byte, the master then sends a command byte that indicates which internal register the master wishes to write. the lTC2945 acknowledges this and then latches the lower six bits of the command byte into its internal register address pointer. the master then delivers the data byte and the lTC2945 acknowledges once more and writes the data into the internal register pointed to by the register address pointer. if the master continues sending additional data bytes with a write word or extended write command, the additional data bytes will be acknowledged by the lTC2945, the register address pointer will automatically increment by one, and data will be written as above. the write operation terminates and the register address pointer resets to 00h when the master sends a stop condition. read protocol the master begins a read operation with a start condition followed by the 7-bit slave address and the r/w bit set to zero. after the addressed lTC2945 acknowledges the address byte, the master then sends a command byte that indicates which internal register the master wishes to read. the lTC2945 acknowledges this and then latches the lower six bits of the command byte into its internal register address pointer. the master then sends a repeated start condition followed by the same 7-bit address with the r/w bit now set to 1. the lTC2945 acknowledges and sends the contents of the requested register. the transmission terminates when the master sends a stop condition. if the master acknowledges the transmitted data byte, as in a read word command, the lTC2945 will send the contents of the next register. if the master keeps acknowledging, the lTC2945 will keep incrementing the register address pointer and sending out data bytes. the read operation terminates and the register address pointer resets to 00h when the master sends a stop condition. alert response protocol when any of the fault bits in the fault register are set, a bus alert is generated if the appropriate bit in the alert register has been set. this allows the bus master to select which faults will generate alerts. at power-up, the alert register is cleared (no alerts enabled) and the alert pin is high. if an alert is enabled, the corresponding fault causes the alert pin to pull low. the bus master responds to the alert in accordance with the smbus alert response protocol by broadcasting the alert response address (0001100)b, and the lTC2945 replies with its own address and releases its alert pin as shown in figure 12. the alert line is also released if the fault or fault cor registers are read (see table 2) since the faulting event can be identified by the content in these registers. the alert signal is not pulled low again until the fault register indicates a different fault has occurred or the original fault is cleared and it occurs again. note that this means repeated or continuing faults will not generate additional alerts until the associated fault register bits have been cleared. lTC2945 2945fa
18 for more information www.linear.com/lTC2945 a pplica t ions i n f or m a t ion if two or more lTC2945s on the same bus are generating alerts when the ara is broadcasted, the bus master will repeat the alert response protocol until the alert line is released. the device with the highest priority (lowest address) will reply first and the device with the lowest priority (highest address) will reply last. r shunt can then be calculated using equation 1. note that both lTC2945 and lTC2945-1 can be used in the shunt regulator applications mentioned. figure 16 shows an alternate connection for use with low- speed opto-couplers and the lTC2945-1. this circuit uses a limited-current pullup on the internally clamped sdai pin and clamps the sdao pin with the input diode of the outgoing opto-isolator, removing the need to use intv cc for biasing in the absence of an auxiliary low voltage sup - ply. for proper clamping: v s(max ) C 5.9v 5ma r4 v s(min) C 6.9v 0.5ma as an example, a supply that operates from 36v to 72v would require the value of r4 to be between 13k and 58k. the lTC2945-1 must be used in this application to ensure that the sdao signal polarity is correct. the lTC2945-1 can also be used with high-speed opto- couplers with push-pull outputs and inverted logic as shown in figure 17. the incoming opto-isolator draws power from the intv cc , and the data output is connected directly to the sdai pin with no pullup required. ensure the current drawn does not exceed the 10ma maximum capability of the intv cc pin. the sdao pin is connected to the cathode of the outgoing optocoupler with a current limiting resistor connected back to intv cc . an additional discrete n-channel mosfet is required at the output of the outgoing optocoupler to provide the open-drain pull - down that the i 2 c bus requires. finally, the input of the incoming opto-isolator is connected back to the output as in the low-speed case. layout considerations a kelvin connection between the sense resistor r sns and the lTC2945 is recommended to achieve accurate current sensing (figure 18). the recommended minimum trace width for 1oz copper foil is 0.02 per amp to ensure the trace stays at a reasonable temperature. using 0.03 per amp or wider is preferred. note that 1oz copper exhibits a sheet resistance of about 530? per square. figure 12. lTC2945 serial bus sda alert response protocol s alert response address 0 0 0 1 1 0 0 device address a7:a0 1 1 r 0 2945 f12 a a p opto-isolating the i 2 c bus opto-isolating a standard i 2 c device is complicated by the bidirectional sda pin. the lTC2945/lTC2945-1 minimize this problem by splitting the standard i 2 c sda line into sdai (input) and sdao (output, lTC2945) or sdao (inverted output, lTC2945-1). the scl is an input only pin and does not require special circuitry to isolate. for conventional non-isolated i 2 c applications, use the lTC2945 and tie the sdai and sdao pins together to form a standard i 2 c sda pin. low speed isolated interfaces that use standard open- drain opto-isolators typically use the lTC2945 with the sdai and sdao pins separated as shown in figure 13. connect sdai to the output of the incoming opto-isolator with a pullup resistor to intv cc or a local 5v supply; con - nect sdao to the cathode of the outgoing opto-isolator with a current-limiting resistor in series with the anode. the input and output must be connected together on the isolated side of the bus to allow the lTC2945 to participate in i 2 c arbitration. note that maximum i 2 c bus speed will generally be limited by the speed of the opto-couplers used in this application. both low and high side shunt regulators can supply up to 34ma of current to drive opto-isolator and pullup resis - tors as shown in figure 14 and 15. for identical sdai/scl pullup resistors the maximum load is: i load(max) = 6.7 2 r1 + 1 r3 ? ? ? ? ? ? (2) (3) lTC2945 2945fa
19 for more information www.linear.com/lTC2945 a pplica t ions i n f or m a t ion figure 13. opto-isolation of a 10khz i 2 c interface between lTC2945 and microcontroller (scl omitted for clarity) figure 14. low speed 10khz opto-isolators powered from low-side shunt regulator figure 15. low speed 10khz opto-isolators powered from high-side shunt regulator lTC2945 sdai sdao gnd 3.3v gnd sda p 1/2 mocd207m 1/2 mocd207m 5v r4 10k r5 0.82k r6 0.51k r7 10k v dd 2945 f13 lTC2945 sdai sdao gnd gnd 3.3v gnd sda p 1/2 mocd207m 1/2 mocd207m r3 1k r1 10k r2 0.51k r4 10k v dd r shunt 2945 f14 r sns 0.02 sense ? sense + intv cc v dd c1 1f v out v ee v ee lTC2945-1 sdai sdao gnd 3.3v gnd sda p 1/2 mocd207m 1/2 mocd207m r3 1k r1 10k r2 1k r4 10k v dd r shunt v out v in 2945 f15 r sns 0.02 sense + sense ? intv cc v dd c1 1f lTC2945 2945fa
20 for more information www.linear.com/lTC2945 a pplica t ions i n f or m a t ion v in 48v 1/2 acpl-064l* 1/2 acpl-064l* * cmos output iso_sda c 1 1f c2 1f r5 2k v dd intv cc lTC2945-1 sdao sdai gnd v cc v cc gnd gnd bs170 m1 r6 2k r7 2k 2945 f17 3.3v gnd sda p v dd figure 16. opto-isolation of a 1.5khz i 2 c interface between lTC2945-1 and microcontroller (scl omitted for clarity) figure 17. opto-isolation of i 2 c interface with low power, high speed opto-couplers (scl omitted for clarity) lTC2945-1 sdai sdao gnd 3.3v gnd sda p 1/2 mocd207m 1/2 mocd207m 48v r4 20k r5 7.5k r6 0.51k r7 10k v dd 2945 f16 figure 18. recommended layout for kelvin connection 10 9 6 7 8 4 5 11 3 2 1 12 v in r sns to load sense + sense ? 2945 f18 lTC2945 2945fa
21 for more information www.linear.com/lTC2945 a pplica t ions i n f or m a t ion table 1. lTC2945 device addressing description hex device address binary device address l TC2945 address pins h a6 a5 a4 a3 a2 a1 a0 r/ w adr1 adr0 mass write cc 1 1 0 0 1 1 0 0 x x alert response 19 0 0 0 1 1 0 0 1 x x 0 ce 1 1 0 0 1 1 1 x h l 1 d0 1 1 0 1 0 0 0 x nc h 2 d2 1 1 0 1 0 0 1 x h h 3 d4 1 1 0 1 0 1 0 x nc nc 4 d6 1 1 0 1 0 1 1 x nc l 5 d8 1 1 0 1 1 0 0 x l h 6 da 1 1 0 1 1 0 1 x h nc 7 dc 1 1 0 1 1 1 0 x l nc 8 de 1 1 0 1 1 1 1 x l l table 2. lTC2945 register addresses and contents register address register name read/write description default 00h control (a) r/w controls adc operation mode and test mode 05h 01h alert (b) r/w selects which faults generate alerts 00h 02h status (c) r system status information 00h 03h fault (d) r/w fault log 00h 04h fault cor (e) cor same data as register d, d content cleared on read 00h 05h power msb2 r/w** power msb2 data xxh 06h power msb1 r/w** power msb1 data xxh 07h power lsb r/w** power lsb data xxh 08h max power msb2 r/w** maximum power msb2 data 00h 09h max power msb1 r/w** maximum power msb1 data 00h 0ah max power lsb r/w** maximum power lsb data 00h 0bh min power msb2 r/w** minimum power msb2 data ffh 0ch min power msb1 r/w** minimum power msb1 data ffh 0dh min power lsb r/w** minimum power lsb data ffh 0eh max power threshold msb2 r/w maximum power threshold msb2 to generate alert ffh 0fh max power threshold msb1 r/w maximum power threshold msb1 to generate alert ffh 10h max power threshold lsb r/w maximum power threshold lsb to generate alert ffh 11h min power threshold msb2 r/w minimum power threshold msb2 to generate alert 00h 12h min power threshold msb1 r/w minimum power threshold msb1 to generate alert 00h 13h min power threshold lsb r/w minimum power threshold lsb to generate alert 00h 14h sense msb r/w** sense msb data xxh 15h sense lsb r/w** sense lsb data x0h 16h max sense msb r/w** maximum sense msb data 00h lTC2945 2945fa
22 for more information www.linear.com/lTC2945 a pplica t ions i n f or m a t ion 17h max sense lsb r/w** maximum sense lsb data 00h 18h min sense msb r/w** minimum sense msb data ffh 19h min sense lsb r/w** minimum sense lsb data foh 1ah max sense threshold msb r/w maximum sense threshold msb to generate alert ffh 1bh max sense threshold lsb r/w maximum sense threshold lsb to generate alert foh 1ch min sense threshold msb r/w minimum sense threshold msb to generate alert 00h 1dh min sense threshold lsb r/w minimum sense threshold lsb to generate alert 00h 1eh v in msb r/w** adc v in msb data xxh 1fh v in lsb r/w** adc v in lsb data x0h 20h max v in msb r/w** maximum v in msb data 00h 21h max v in lsb r/w** maximum v in lsb data 00h 22h min v in msb r/w** minimum v in msb data ffh 23h min v in lsb r/w** minimum v in lsb data foh 24h max v in threshold msb r/w maximum v in threshold msb to generate alert ffh 25h max v in threshold lsb r/w maximum v in threshold lsb to generate alert foh 26h min v in threshold msb r/w minimum v in threshold msb to generate alert 00h 27h min v in threshold lsb r/w minimum v in threshold lsb to generate alert 00h 28h adin msb r/w** adin msb data xxh 29h adin lsb r/w** adin lsb data x0h 2ah max adin msb r/w** maximum adin msb data 00h 2bh max adin lsb r/w** maximum adin lsb data 00h 2ch min adin msb r/w** minimum adin msb data ffh 2dh min adin lsb r/w** minimum adin lsb data foh 2eh max adin threshold msb r/w maximum adin threshold msb to generate alert ffh 2fh max adin threshold lsb r/w maximum adin threshold lsb to generate alert foh 30h min adin threshold msb r/w minimum adin threshold msb to generate alert 00h 31h min adin threshold lsb r/w minimum adin threshold lsb to generate alert 00h *register address msbs b7-b6 are ignored. ** writable if bit a4 is set lTC2945 2945fa
23 for more information www.linear.com/lTC2945 a pplica t ions i n f or m a t ion table 3. control register a (00h) - read/write bit name operation a7 adc snapshot mode enable enables adc snapshot mode; 1 = snapshot mode enabled. only channel selected by a6 and a5 is measured by the adc. after the conversion, the busy bit is reset and the adc is halted. 0 = snapshot mode disabled (continuous scan mode. default) a6 adc channel label for snapshot mode adc channel label for snapshot mode a6 a5 adc channel 0 0 sense (default) 0 1 v in 1 0 adin a5 a4 test mode enable test mode halts adc operation and enables writes to internal adc/logic registers; 1 = enable test mode, 0 = disable test mode (default) a3 adc busy in snapshot mode adc current status; 1 = adc converting, 0 = adc conversion completed (default), not writable a2 v in monitor enables v dd or sense + voltage monitoring; 1 = monitor sense + voltage (default), 0 = monitor v dd voltage a1 shutdown enable enables low-i q / shutdown mode; 1 = enable shutdown, 0 = normal operation (default) a0 multiplier select selects adin or sense + /v dd (depends on a2) data for digital multiplication with sense data; 1 = select sense + /v dd (default), 0 = select adin table 4. alert register b (01h) - read/write bit name operation b7 maximum power alert enables alert when power calculation data is > maximum power threshold; 1 = enable alert, 0 = disable alert (default) b6 minimum power alert enables alert when power calculation data is < minimum power threshold; 1 = enable alert, 0 = disable alert (default) b5 maximum sense alert enables alert when adc sense measurement data is > maximum sense threshold; 1 = enable alert, 0 = disable alert (default) b4 minimum sense alert enables alert when adc sense measurement data is < minimum sense threshold; 1 = enable alert, 0 = disable alert (default) b3 maximum v in alert enables alert when adc v in measurement data is > maximum v in threshold; 1 = enable alert, 0 = disable alert (default) b2 minimum v in alert enables alert when adc v in measurement data is < minimum v in threshold; 1 = enable alert, 0 = disable alert (default) b1 maximum adin alert enables alert when adc adin measurement data is > maximum adin threshold; 1 = enable alert, 0 = disable alert (default) b0 minimum adin alert enables alert when adc adin measurement data is < minimum adin threshold; 1 = enable alert, 0 = disable alert (default) lTC2945 2945fa
24 for more information www.linear.com/lTC2945 a pplica t ions i n f or m a t ion table 5. status register c (02h) - read bit name operation c7 power overvalue present indicates power overvalue when power is > maximum power threshold; 1 = power overvalue, 0 = power not overvalue c6 power under value present indicates power undervalue when power is < minimum power threshold; 1 = power undervalue, 0 = power not undervalue c5 sense over value present indicates sense over value when sense is > maximum sense threshold; 1 = sense overvalue, 0 = sense not overvalue c4 sense under value present indicates sense under value when sense is < minimum sense threshold; 1 = sense undervalue, 0 = sense not undervalue c3 v in overvalue present indicates v in overvalue when v in is > maximum v in threshold; 1 = v in overvalue, 0 = v in not overvalue c2 v in undervalue present indicates v in undervalue when v in is < minimum v in threshold; 1 = v in undervalue, 0 = v in not undervalue c1 adin overvalue present indicates adin overvalue when adin is > maximum adin threshold; 1 = adin overvalue, 0 = adin not overvalue c0 adin under value present indicates adin undervalue when adin is < minimum adin threshold; 1 = adin undervalue, 0 = adin not undervalue table 6. fault register d (03h) - read/write bit name operation d7 power overvalue fault occurred indicates power overvalue fault when power was > maximum power threshold; 1 = power overvalue fault occurred, 0 = no power overvalue faults d6 power under value fault occurred indicates power under value fault when power was < minimum power threshold; 1 = power undervalue fault occurred, 0 = no power undervalue faults d5 sense over value fault occurred indicates sense over value fault when sense was > maximum sense threshold; 1 = sense overvalue fault occurred, 0 = no sense overvalue faults d4 sense under value fault occurred indicates sense under value fault when sense was < minimum sense threshold; 1 = sense undervalue fault occurred, 0 = no sense undervalue faults d3 v in overvalue fault occurred indicates v in overvalue fault when v in was > maximum v in threshold; 1 = v in overvalue fault occurred, 0 = no v in overvalue faults d2 v in undervalue fault occurred indicates v in undervalue fault when v in was < minimum v in threshold; 1 = v in undervalue fault occurred, 0 = no v in undervalue faults d1 adin overvalue fault occurred indicates adin overvalue fault when adin was > maximum adin threshold; 1 = adin overvalue fault occurred, 0 = no adin overvalue faults d0 adin under value fault occurred indicates adin under value fault when adin was < minimum adin threshold; 1 = adin undervalue fault occurred, 0 = no adin undervalue faults lTC2945 2945fa
25 for more information www.linear.com/lTC2945 a pplica t ions i n f or m a t ion table 9. power, min/max power, min/max power threshold register data format: msb2 bytes- read/write* bit (7) bit (6) bit (5) bit (4) bit (3) bit (2) bit (1) bit (0) data (23) data (22) data (21) data (20) data (19) data (18) data (17) data (16) * set bit a4 before writing to power and min/max power registers table 10. power, min/max power, min/max power threshold register data format: msb1 bytes- read/write* bit (7) bit (6) bit (5) bit (4) bit (3) bit (2) bit (1) bit (0) data (15) data (14) data (13) data (12) data (11) data (10) data (9) data (8) * set bit a4 before writing to power and min/max power registers table 8. adc, adc min/max, min/max threshold register data format: lsb bytes-read/write* bit (7) bit (6) bit (5) bit (4) bit (3) bit (2) bit (1) bit (0) data (3) data (2) data (1) data (0) reserved** reserved** reserved** reserved** * set bit a4 before writing to adc and min/max adc registers ** read as 0 table 7. adc, adc min/max, min/max adc threshold register data format: msb bytes-read/write* bit (7) bit (6) bit (5) bit (4) bit (3) bit (2) bit (1) bit (0) data (11) data (10) data (9) data (8) data (7) data (6) data (5) data (4) *set bit a4 before writing to adc and min/max adc registers table 11. power, min/max power, min/max power threshold register data format: lsb bytes- read/write* bit (7) bit (6) bit (5) bit (4) bit (3) bit (2) bit (1) bit (0) data (7) data (6) data (5) data (4) data (3) data (2) data (1) data (0) * set bit a4 before writing to power and min/max power registers lTC2945 2945fa
26 for more information www.linear.com/lTC2945 typical a pplica t ions a wide range supply monitor 2945 ta02 2.7v to 5.9v c2 0.1f v in 0v to 80v r sns 0.02 v out v adin r1 2k r2 2k r3 2k 3.3v v dd scl sda int gnd adr0 scl v dd intv cc sdai sdao adin alert adr1 sense + gnd sense ? lTC2945 p 2945 ta03 v in 4v to 80v c2 0.1f r sns 0.02 v out v adin r1 2k r2 2k r3 2k 3.3v v dd scl sda int gnd adr0 scl v dd intv cc sdai sdao adin alert adr1 sense + gnd sense ? lTC2945 p wide range supply monitor with wide range v dd input dual supply monitor with common opto-coupler for galvanic isolation v adin1 v adin2 v in1 24v v cc1 v cc2 v cc2 v cc1 v in2 48v r sns1 0.02 r sns2 0.02 r4 10k r5 10k r6 1k r7 1k r8 0.51k r9 0.51k r10 10k r11 10k r12 10k v out1 v out2 c1 1f c2 0.1f c3 1f c4 0.1f adr0 scl v dd intv cc sdai sdao adin alert adr1 sense + sense ? lTC2945 hcpl063l hcpl063l 3.3v scl sda v dd int gnd p adr0 scl v dd intv cc sdai sdao adin alert adr1 sense + gnd gnd sense ? lTC2945 2945 ta04 v cc v cc 3.3v gnd gnd lTC2945 2945fa
27 for more information www.linear.com/lTC2945 power monitoring in C48v system using low side sensing (1.5khz i 2 c interface) typical a pplica t ions c1 1f control register a2 = 0 mocd207m mocd207m 2945 ta05 adr0 adr1 scl v dd intv cc v ee sdai sdao adin alert sense ? gnd sense + lTC2945 c2 0.1f ?48v rtn v ee ?48v input r7 0.51k r3 1k r4 1k v out r8 0.51k r9 10k r10 10k r11 10k 3.3v r sns 0.02 v dd gnd p scl sda int r1 20k r2 20k v cc gnd r shunt 3 1.8k in series c1 1f hcpl-063l control register a0 = 0 v ee v ee hcpl-063l 2945 ta06 adr0 adr1 scl v dd intv cc sdai sdao adin alert sense ? gnd sense + lTC2945 v cc gnd ?48v rtn v ee ?48v input r7 0.51k r3 0.51k r4 1k v out c2 1f r8 0.51k r9 1k r10 1k r11 10k 3.3v 3.3v r sns 0.02 v dd gnd p scl sda int r12 100 q1 pzta42 d1 1n4148ws r1 1k r2 1k r5 735k r6 15k power monitoring in C48v harsh environment using intv cc shunt regulator to tolerate 200v transients lTC2945 2945fa
28 for more information www.linear.com/lTC2945 typical a pplica t ions power monitoring in C48v system using external linear regulator to supply opto-couplers and scl/sda resistive pull-ups wide range dual supply monitor with single lTC2945 v cc gnd c1 1f ps9817-2 control register a2 = 0 v ee ps9817-2 2945 ta07 adr0 adin adr1 scl v dd intv cc v ee sdai sdao alert sense ? gnd sense + lTC2945 lt3010-5 v cc gnd ?48v rtn v ee ?48v input r7 0.5k r3 0.51k r4 1k v out r8 0.51k r9 1k r10 1k r11 10k 5v 5v r sns 0.02 v dd gnd p scl sda int r1 1k r2 10k in shdn out sense gnd c3 0.1f c2 1f * select rshunt according to the equation in the ?flexible power supply to lTC2945? section. ** voltage data has an offset value due to d1?s drop, if desirable this can be compensated through software. r adin 20k 2945 ta08 r sns 0.02 c3 0.1f c2 0.1f adr0 adr1 v dd intv cc sdai scl sdao alert adin sense + gnd sense ? lTC2945 ltc6102 r in2 1k r shunt* d2 bat54 d1 bat54 r in1 1k c1 0.1f r sns1 0.02 v + v ? v reg ?inf ?ins out +in supply b 4.5v to 80v supply a 4.5v to 80v i 2 c interface to load supply a sense + ?sense internally generated use external p to multiply voltage (v dd ) and current (adin) data adin v dd ** 1 voltage d ata current d ata power d ata control reg a2 0 supply b lTC2945 2945fa
29 for more information www.linear.com/lTC2945 ruggedized 4v to 70v high side power monitor with surge protection up to 200v isolated wide range i 2 c power monitor typical a pplica t ions v cc gnd c1 0.1f hcpl-063l fgnd hcpl-063l 2945 ta09 adr1 adr0 adin scl v dd v in v out intv cc sdai sdao alert sense + gnd sense ? lTC2945 v cc gnd r7 0.51k r3 0.51k r12 100 r4 1k fgnd fgnd c2 1f r8 0.51k r9 1k r10 1k r11 10k 3.3v 3.3v r sns 0.02 v dd gnd p scl sda int t1 smaj70a diodes, inc q1 pzta42 r1 1k r5 1 m1 bsp149 r2 1k 2945 ta09a 1f 3.3v 10k 10k v in 0v to 80v v out r sns 0.02 v adin v cc v l on gnd di1 sda scl dnc do2 do1 gnd v dd intv cc adr0 adr1 adin alert sdao sdai scl sense + gnd scl2 sda2 o1 av ? av + v ? v + av cc2 v cc2 i2 dnc i1 gnd2 sense ? lTC2945 ltm2883-3i scl int sda v cc gnd p c2 0.1f r2 10k lTC2945 2945fa
30 for more information www.linear.com/lTC2945 typical a pplica t ions wide range C4v to C500v negative power monitor (10khz i 2 c interface) v ee v ee c2 0.1f control register a2 = 0 mocd207m mocd207m 2945 ta10 adr0 adr1 adin scl v dd intv cc sdai sdao alert sense ? gnd sense + lTC2945 c1 0.1f v ee r7 0.51k r3 1k r13 10k m1 bsp135 r4 1k v out r8 0.51k r9 10k r10 10k r11 10k 3.3v r sns 0.02 v dd gnd p scl sda int r1 2k r2 2k r12 5k r6 750k z1 4.7v r5 750k rtn lTC2945 2945fa
31 for more information www.linear.com/lTC2945 p ackage descrip t ion msop (ms12) 0213 rev a 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ?0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 11 10 9 8 7 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) ms package 12-lead plastic msop (reference ltc dwg # 05-08-1668 rev a) lTC2945 2945fa
32 for more information www.linear.com/lTC2945 ud package 12-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1855 rev ?) p ackage descrip t ion 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions 1.65 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.65 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 11 12 2 0.50 bsc 0.200 ref 2.10 0.05 3.50 0.05 0.70 0.05 0.00 ? 0.05 (ud12) qfn 0709 rev ? 0.25 0.05 0.50 bsc package outline lTC2945 2945fa
33 for more information www.linear.com/lTC2945 r evision h is t ory rev date description page number a 09/13 added limits to full-scale voltage removed note 5 from i 2 c interface timing added note 5 to scl, sdai input capacitance added adin and resistive divider information with regards to figure 3a and figure 3c revised figure 3a and figure 3c revised figure 13 and figure 17 revised bottom figure top figure: replaced smaj78a with smaj70a and changed c2 connection from vee to fgnd added isolated wide range i 2 c power monitor figure 4 5 5 12 13 19, 20 26 29 29 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. lTC2945 2945fa
34 for more information www.linear.com/lTC2945 r ela t e d p ar t s typical a pplica t ion part number description comments ltc4151 high voltage i 2 c current and voltage monitor 7v to 80v operation, 12-bit resolution with 1.25% tue lt6105 rail-to-rail input current sense amplifier very wide input common mode range, 2.85v to 36v operation ltc2450 easy-to-use, ultra-tiny 16-bit adc gnd to v cc single-ended input range, 0.02 lsb rms noise, 2 lsb inl (no missing codes), 2 lsb offset error, 4 lsb full-scale error l tc4215 single channel, hot swap controller with i 2 c monitoring 8-bit adc, adjustable current limit and inrush, 2.9v to 15v operation ltc4222 dual channel, hot swap controller with i 2 c monitoring 10-bit adc, adjustable current limit and inrush, 2.9v to 29v operation ltc4260 positive high voltage hot swap controller with i 2 c monitoring 8-bit adc, adjustable current limit and inrush, 8.5v to 80v operation ltc4261 negative high voltage hot swap controller with i 2 c monitoring 10-bit adc, floating topology, adjustable inrush ltc2940 power and current monitor four-quadrant multiplication, 5% power accuracy, 4v to 80v operation ltc2970 dual i 2 c power supply monitor and margining controller 14-bit adc with 0.5% tue, dual 8-bit dacs ltc2974 quad digital power supply manager with eeprom 16-bit adc with 0.25% tue, supervise/sequence/monitor/margin/ trim, configuration/fault logging eeprom, i 2 c, supervise/monitor current and temperature ltc2978 octal digital power supply manager with eeprom 16-bit adc with 0.25% tue, supervise/sequence/monitor/margin/ trim, configuration/fault logging eeprom, i 2 c rail-to-rail bidirectional current and power monitor 3.3v input supply monitor with 12v v dd input v + in ? in + v ? lt6105 2.7v to 5.9v v out v in 0v to 44v sense + sense ? alert scl sdai adin adr0 adr1 lTC2945 sdao intv cc v dd r sns 0.02 r in1 1k r in2 1k to load r adin 20k i 2 c interface 2945 ta11 gnd forward sense + ?sense internally generated use external p to multiply voltage (sense + ) and current (adin) data adin sense + 1 voltage d ata current d ata power d ata control reg a2 1 reverse c2 0.1f r1 2k r2 2k r3 2k v in 3.3v 3.3v 12v r sns 0.02 v out v dd v adin v dd adr0 intv cc sense + gnd gnd 2945 ta12 sense ? lTC2945 adr1 scl scl sda sdai sdao adin alert int p ? linear technology corporation 2012 lt 0913 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lTC2945 lTC2945 2945fa

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